Welcome to the Bioinspired Integrated Circuit (BIC) Design Lab. Dr. Mohammad Haider joined the Electrical and Computer Engineering department as an Assistant Professor in 2011. He is the lab director of ‘Bioinspired Integrated Circuit Design (BIC)’ lab and ‘Analog Electronics’ lab. Dr Haider is also serving as the university academic liaison of MOSIS Educational Program (MEP) and Cadence University Program. Dr. Haider's research interests include low-power analog and RF integrated circuit and system design for wireless implantable/wearable/portable device applications. He has more than 10 years of integrated circuit (IC) design experience. Dr. Haider was involved in low-power electronics development for implantable glucose sensor and MEMS-based capacitive pressure sensor. At present, Dr. Haider's research group is focused on bringing the energy-efficient design concepts from nature and developing biologically-inspired or bio-inspired integrated circuits for ultra-low-power electronics development.
   Low-power electronics is extremely important for long-term, reliable operation and minimum battery-replacements of implantable or portable devices. Future trend is directing towards the development of ultra-low-power electronics for signal processing and wireless telemetry, and running the electronics by the energy harvested from the environment. Dr. Haider's group is investigating innovative applications of ultra-low-power implantable or portable devices for civil, medical, military, and space applications. In BIC lab, we focus on design, modeling, fabrication and experimental validation of low-power analog-RF circuit and system, wireless power transfer, bioinspired analog VLSI circuit architecture, short range wireless telemetry, injection-locking and injection-locked transmitter architectures, orthogonal UWB communication, on-chip analog signal processing, etc. In our lab, we perform both schematic level and post-layout level simulation, and fabricate our custom integrated circuits and systems using standard CMOS processes (for device gate lengths of 130 nm, 180 nm, and 0.5 µm) under MOSIS Educational Program.